| dc.contributor.author | GREGG, DAVID | |
| dc.contributor.author | WILSON, SIMON PAUL | |
| dc.date.accessioned | 2009-09-18T16:47:12Z | |
| dc.date.available | 2009-09-18T16:47:12Z | |
| dc.date.created | 7-10 Aug | en |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005 | en |
| dc.identifier.citation | Bannister, R. Gregg, D. Wilson, S. Nisbet, A. `FPGA implementation of an Image Segmentation algorithm using logarithmic arithmetic? in Proceedings of the Midwest Symposium on Circuits and Systems, KY, 7-10 Aug, 2005, 2005, pp 810-813 | en |
| dc.identifier.other | Y | |
| dc.identifier.other | Y | en |
| dc.identifier.uri | http://hdl.handle.net/2262/32974 | |
| dc.description | PUBLISHED | en |
| dc.description.abstract | Image Segmentation is a process used in Computer
Vision to automatically divide up an image. We investigate the
suitability of FPGAs and Log Arithmetic for Image Processing.
We implemented a Bayesian pixel-based segmentation
algorithm in hardware, and found that certain portions of the
algorithm running on a mid-range FPGA could significantly
outperform an implementation running on a high-end PC. | en |
| dc.format.extent | 810-813 | en |
| dc.format.extent | 469678 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | en |
| dc.publisher | IEEE | en |
| dc.relation.ispartofseries | 2005 | en |
| dc.rights | Y | en |
| dc.subject | Statistics | en |
| dc.title | FPGA implementation of an Image Segmentation algorithm using logarithmic arithmetic | en |
| dc.type | Conference Paper | en |
| dc.type.supercollection | scholarly_publications | en |
| dc.type.supercollection | refereed_publications | en |
| dc.identifier.peoplefinderurl | http://people.tcd.ie/swilson | |
