Build automation and runtime abstraction for partial reconfiguration on Xilinx Zynq Ultrascale+
Citation:
Bucknall, Alex R., Shreejith, Shanker, Fahmy, Suhaib A., Build automation and runtime abstraction for partial reconfiguration on Xilinx Zynq Ultrascale+, International Conference on Field-Programmable Technology, 9–11 Dec 2020Download Item:
Abstract:
Partial reconfiguration (PR) is fundamental to building adaptive systems on modern FPGA SoCs, where hardware can be adapted dynamically at runtime. Vendor supported reconfiguration is performance limited, drivers entail complex memory management, and software/hardware design requires detailed knowledge of the underlying hardware. This paper presents a collection of abstractions that provide high performance reconfiguration of hardware from within the Linux user space, automating the process of building PR applications,and adding support for the Xilinx Zynq UltraScale+ architecture.We compare our abstractions against vendor tooling for PR management and open source tools supporting PR within Linux.Our tools provides automation and abstraction layers, from defining PR configurations through to compiling and packaging Linux with support for user space PR control, targeted for non-experts.
Sponsor
Grant Number
Engineering and Physical Sciences Research Council (EPSRC)
EP/N509796/1
Author's Homepage:
http://people.tcd.ie/shankersDescription:
PUBLISHED
Author: Shanker, Shreejith
Other Titles:
International Conference on Field-Programmable TechnologyProceedings of the International Conference on Field Programmable Technology
Type of material:
Conference PaperAvailability:
Full text availableSubject (TCD):
Digital Design , Field Programmable Gate Arrays (FPGAs) , VHDL, FPGA, DIGITAL DESIGNMetadata
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